I am not sure who the RISC-V designers expect for their audience, nor why this double standard, but in the light of "the 50 year plan", it appears that the designers haven't given it much thought, if any at all. It is unclear to me why this double-standard is okay: on one hand, that which is really important, like assembler syntax and mnemonics is exposed and yet not considered relevant, but "micro-architectural details" which really don't hurt me as the coder one way or the other should be hidden. However the vast majority of even kernel/embedded programmers rarely touch assembler these days. To the authors of RISC-V:Ĭouldn't you have made the mnemonics MC68000 compatible, or at least make them similar?īecause you shouldn't expose such micro-architectural details in an ISA which is trying to be stable for the next 50 years Oh, and I seriously dislike the instruction mnemonics. We're the only industry that I know of that keeps nuking itself and starting from scratch, throwing away all the work which had been done before. All the lessons about reuse went out of the window. There is already an open source processor design, and a good, solid design, and they just went ahead and invented their own anyway. The last point is their biggest sin, in my view. How does 128-bit support justify starting from scratch, and not re-using what is already there and open sourced? the fact that they could have extended the open source UltraSPARC T-series design, but decided to just re-invent the wheel all over again. the fact that the instruction set is non-orthogonal (32-bit fixed encoding makes the decoder simple, but creates the same load-store problem as on SPARC - hello non-existent, synthetic instructions!) the fact that this processor design is being aggressively pushed here (featured several times already) the assembler dst, src backward syntax (like intel)
I understand that designing processors is fun, but I hold several things against RISC-V:
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